CY7C342B-30RC/RI
| Main description | CPLD MAX® Family 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed CPGA |
|---|
CPLD MAX® Family 128 Macro Cells 50MHz 0.65um Technology 5V 68-Pin Windowed CPGA
Informacje podstawowe
- ProducentCypress Semiconductor
- EURoHSUnknown (2002/95/EC)
- Automotive No
Informacje dodatkowe
- Crosses 10
- PCNs 25
- MaskPart CY7C342B30RCRI%
- IntroductionDate May 29, 1997
- SupplierUrl http://www.cypress.com/?app=search&searchType=part&keywords=CY7C342B-30RC/RI
Parametry
- Clock Management N/A
- Copy Protection Yes
- Data Gate No
- Device Logic Cells N/A
- Device System Gates N/A
- Family Name MAX®
- I/O Voltage (V) N/A
- In-System Programmability No
- Individual Output Enable Control No
- Maximum Clock to Output Delay (ns) 30
- Maximum Internal Frequency (MHz) 50
- Maximum Propagation Delay Time (ns) 30
- Maximum Storage Temperature (°C) 150
- Memory Size (Kbit) N/A
- Minimum Storage Temperature (°C) -65
- Number of Flip Flops 128
- Number of Global Clocks N/A
- Number of I/O Banks N/A
- Number of Inter Dielectric Layers 2
- Number of Logic Blocks/Elements 8
- Number of Macro Cells 128
- Number of Product Terms per Macro 32
- Number of User I/Os 52
- Process Technology 0.65um
- Program Memory Type EPROM
- Programmability Yes
- Programmable Type UV Erasable
- RAM Bits (Kbit) N/A
- Reprogrammability Support No
- Speed Grade 30
- Supplier Temperature Grade Industrial
- Temperature Flag Opr
- Tolerant Configuration Interface Voltage (V) N/A
- Tradename MAX